1. Assume that a silicon transistor with β =50, V_BEactive=0.7 V, V_CC =15V and R_C=10K is used in the Fig.1.It is desired to establish a Q-point at V_CE=7.5 V and I_C=5mA and stability factor S≤5.Find Re,R₁and R₂.

Fig.1

For the curved surface of the cylinder, the unit vector is which gives  Parameterize ,Since we are confined to the first octant The flux through the slant surface is .  The top and the bottom caps are in the  directions, the contribution from these two give zero by symmetry.  There are two more surfaces if we consider the first octant, they are the positive x-z plane and the positive y-z plane., the normal to the former being in the direction of  while that for the latter is along  directions. The flux from the former is , while that from the latter is .  Adding up all the contributions, the total flux from the closed surface is zero. This is consistent with the fact that the divergence of the field is zero.

2. In the Darlington stage shown in Fig.2 , V_CC=15V , β₁=50,  β₂=75,V_BE=0.7,R_C=750 Ω and R_E=100 Ω. If at the quiescent point V_CE2=6V determine the value of R.

Fig.2

There are six faces. For the face at x=0, since the surface is directed along  direction, the surface integral is   The face at x=1 gives +1/2. The faces at y=0 and that at z=0 gives zero because the field is proportional to y and z respectively. The contribution to flux from y=1 is 1 and that from z=1 is 3/2. Adding, the flux is 5/2 units.  This can also be done by the divergence theorem. Divergence of the field is  2x+3y, so that the volume integral is

3. For the amplifier shown in Fig.3 using a transistor whose parameters are h_ie=1100,h_re=2.5×10^-4,h_fe=50,h_oe=24µA/V.Find A_I, A_V, A_VS and R_i.

Fig.3

The divergence of the given vector field is . Thus, by divergence theorem, the flux is  . We can show this result by direct integration. The unit normal on the surface of the sphere is given by  , so that the flux is  This integral can be conveniently evaluated in a spherical polar coordinates with  The surface element on the sphere is  . By symmetry, the flux can be seen to be  . (Note that we decided to do the integral involving z4 rather than x4 or y4 because the azimuthal integral gives 2p in this case.  The integral is easy to perform with the substitution  , which gives the flux to be  .

4. Find the voltage gain A_V , A_VSof the amplifier shown. Assume h_ie =1100 ,h_re=2.5×10^-4, h_fe=50, h_oe=24µA/V. Also find Ri and Ro.

Fig.4

The divergence of the field is 3. The flux, therefore, is  3 times the volume of the cone which is The flux is thus  The  direct calculation of the flux involves two surfaces, the slant surface and the cap, as shown in the figure. The cap is in the xy plane and has an outward normal . The flux (because on the cap z=1 and the cap is a disk of unit radius).  Thus it remains to be shown that the flux from the slanted surface vanishes. At any height z, the section parallel to the cap is a circle of radius z. Since, the height and the radius of the cap are 1 each, the semi angle of the cone is 45⁰.

Thus the normal to the slanted surface has a component  along the z direction and  in the x-y plane. The component in the xy plane can be parameterized by the azimuthal angle  and we can write  . The area element can be written as  , the factor  appears because the length element is along the slant. Thus the contribution from the slanted surface is  . Using  , this integral can be evaluated and shown to be zero.

5. Given the following transistor measurements made at I_C=10mA , V_CE=7.5V and at room temperature h_fe=100 , h_ie =1100 , A_ie=40 at 1MHz and Cc=3 pf. Find f_β , f_T , Ce , r_bꞌe and r_bbꞌ.

This problem is to be attempted similar to the problem  5 of the tutorial, i.e., by closing the cap and subtracting the contribution due to the cap. The divergence being 3, the  flux from the closed cone is 3 times the volume of the cone which gives   The contribution from the top face (which is a disk of  radius 2 ) is . Thus the net flux is zero.  (You can also try to get this result directly as done in problem 4, where we showed that the flux from the curved surface is zero).

6. Determine the voltage gain for the following circuits given in Fig.6.

Fig.6

7. Design the circuit given in Fig.7 for a voltage gain of 30 and a power budget of 15mW. Assume voltage drop across R_s is equal to the overdrive voltage of the transistor and R_D=400 Ω.

Fig.7

8. In the following amplifier circuit shown in Fig.8 small signal output resistance R_out=R_outa//R_outb, where Routais the resistance seen from the drain of M₂ and R_outb is the resistance seen from drain of M₃.

If I_D1=2I_D2

1. Show that only depends on the ratio of gate overdrive voltage of M₂ & M₃.
2. Determine the bias currents and size of all transistors if the following constraints are considered.Bias all the transistors in the saturation region. I_D2=100µA ,V_GST3=3V_GS2, .Minimum voltage gain of 5000.
3. Determine

Fig.8

9. The current mirror shown in the Fig.9 should satisfy the following conditions.

• 
• 

for all transistors . Iref =1µA,Iout=10µA.Gate overdrive V_GST=200mV for M₁and M₂.

1. Find Vbias and size of all transistors such that V_outmin can reach to its minimum possible value if V_GSTmin=150mV for M₃ & M₄.Determine minimum possible value of V_outmin.
2. Find output resistance of current mirror.

Fig.9

10. Design the commongate stage of the given circuit in Fig.10 which employs the current source M₃ as the load to achieve a voltage gain .Neglect λ of M₁ . Assuming M₃= 400/1 , λn=0.1V^-1 , λp = 0.2 V^-1,design the circuit for a voltage gain of 100 an input impedance of 200 Ω and a power budget of 30mW.

Fig.10

11. Due to manufacturing error,a parasitic resistance R_P has appeared in series with the source of M₁ as shown in figure . Assume λ =0.Detremine the input and output poles of the circuit and plot the bode diagram.

Fig.11

12. Construct the bodeplot of and find the poles and zeroes.

---

Fig.12

13. Design a PMOS differential  amplifier for  the following specifications. =100 , I_REF=I=500µA . The dc voltage at the gates of M₆ and M₇ is 2.5V. The DC voltage at the gate of M₇ , M₄ and M₅ is -2.5 V . The µ_nCox= 3µ_pCox=120µA/ V², Vtn=|Vtp|= 0.7V ,= ||=30V.

1. Find the value of R & W/L ratios of all transistors. Find A_d and A_c.
2. Find the input commonmode range.
3. Find the allowable range of the output voltage.

Fig.13

14. For the given circuit in Fig.14 draw the half circuit for both differential and common mode and compute both differential and common mode gain.

Fig.14

15. For the given circuit in Fig.15 draw the half circuit for both differential and commonmode and compute both differential and common mode gain.

Fig.15

16. A typical differential Amplifier shown in Fig.16 has interesting combination of loads which is parallel combination of current source load and diode connected load. Evaluate V_out =V₀₁ - V₀₂ and differential gain A_vdm.Given λn =0.04/V,λp=0.06/V , M₁= M₂=50/0.5 ,Iss=5mA, βnꞌ=50uA/V² βpꞌ=16µA/V²,M₃=M₄=10/0.5,M₅=M₆=40/0.5.What would have been A_vdm value if the loads are only diode connected load instead of M₃ & M₅ combination.

Fig.16

17. Design all of the W/L values of every transistor of this opamp to meet the following specifications :

Find differential gain, power dissipation and V_Bp & V_Bn. SR= ±20V/µs , =3V , =0.8V,  =1.2V , =3V and GB=40MHz.

Fig.17

18. . In the two stage feedback amplifier shown in Fig.18 , the transistors are identical and have h_fe=100 and h_re=10K Ω, h_re=0and h_oe =0.Calculate

i)A_if=Io/Is

ii)R_if=Vi/Is

iii)Aꞌ_if=Io/Iiꞌ,

iv)A_vf=Vo/Vs where Vs=IsRs

Fig.18

19. For the given circuit shown in Fig.19 ,assume λ =0

1. Find the type of feedback.
2. Assume R_F is very large and breaking the loop at the gate of M₂ , Calculate the loop gain and prove what type of feedback it is .
3. If Io is replaced by R_L, find the closed loop input and output impedances of the circuit.

Fig.19

20. Consider the feedback circuit shown in Fig.20, assume V_A=α

1. Suppose the output quantity of interest is the collector current of Q₂,I_out.Assuming R_M is very small and R_F is very large determine the closed loop gain and input and output impedances of the circuit.
2. Now suppose the output quantity of interest is Vout. Assume R_F is very large, compute the closed loop gain, input and output impedances of the circuit .

Fig.20

21. For the given circuits

1. Calculate the loopgain.
2. Find the closed loop gain.Assume the opamp exhibits an open loop gain of A₁.

Fig.21

22. . Design an opamp circuit to provide an outputVo = -(6V1+  + . Choose relatively low values of resistances but ones for which the input current (from each input signal source) does not exceed 0.1mAfor 1V input signal.

23. For the given circuit in Fig.23 find .

Fig.23

24. For the given opamp circuit in Fig.24

1. Find the input impedance.
2. Design the resistance values for a gain of 1000 with Ri=α.

Fig.24

25. Design a bandpass filter with f_o=1MHz and Q=10 and unity resonance gain. Find H_OBP,ω_O and Q for C₁=C₂=Cand R₁=R₂=R.

Fig.25

26. The circuit shown in Fig.26 uses a summing amplifier A₁ and a bandpass stage A₂ to increase the Q of the bandpass stage without changing ω_o.This allows for high Q_S without unduly taxing A₂.

1. Show that the gain and Q of the composite circuit are related to those of the basic band pass stage as  and
2. Specify component values for =4000Hz =100 and (Comp) =10 starting with Q=10.

Fig.26

27. We wish to design a quartz crystal oscillator of frequency 2 MHz. Draw equivalent resonant tuned circuit for such crystal. If and series resonant . Evaluate  and Q. The crystal is to be used in colpitt oscillator. In that configuration the MOS transistor is biased to 2 mA. We have  =100 .Evaluate value of resistance R shunting across drain and source of transistor and value of . The colpitts oscillator with quartz crystal has the circuit as shown in Fig.27. Assume = 0.02 pf.

Fig.27